FPGA implementation of wearable ECG system for detection premature ventricular contraction
In recent years, wearable electrocardiogram system (WES) has entered the technology market, allowing physicians to instantaneously know about the patient's condition. Hardware is required for creating a wearable and portable electrocardiogram (ECG) system. Field programmable gate arrays (FPGAs) provide fast test capability and have sufficient flexibility to implement new algorithms.. In this study, with regard to the fact that wearable tools of power consumption, accuracy of detection, and price of chips are significant factors in their performance, premature ventricular contractions (PVC) arrhythmic detection and algorithms of the electrocardiogram are studied by presenting three various algorithms in time domain, frequency and time combination of frequency as well as their implementation on FPGA. For each of the three algorithms in this design, the support vector machine(SVM) and the naive bayes(NB) were used after the ECG signal pre-processing and the extraction of the appropriate features of the two classes and the data were categorized as normal and PVC. Extracting features was conducted by the reconfiguration PAT algorithm in the time domain, the Haar wavelet algorithm in the frequency domain and combining these two algorithms. The desired algorithms were tested by the MIT-BIH database and the system performance is achieved with 99% accuracy using SVM. The best algorithm for a WES was obtained in terms of power, price, detection time, accuracy, and sensitivity of the reconfiguration of PAT algorithm on implementation of SPARTAN6 with a performance of 13.6u.
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